Verilog Assignments

In Verilog, assignments are used to drive values into nets and variables. They are categorized into three main types based on how and where they are used.

1. Continuous Assignments

Continuous assignments drive values onto nets (e.g., wire). They are always active; whenever an operand on the right-hand side (RHS) changes, the left-hand side (LHS) is updated immediately.

• Syntax: Uses the assign keyword outside of procedural blocks.

• Usage: Modeling combinational logic.

Verilog

// Example: Simple AND gate
wire a, b, out;
assign out = a & b; 

// Example: Using a conditional (ternary) operator
wire [1:0] sel;
wire [3:0] d0, d1, mux_out;
assign mux_out = (sel == 2'b01) ? d0 : d1;

2. Procedural Assignments

Procedural assignments occur within procedural blocks like initial and always. They update the value of variables (e.g., reg, integer) and hold that value until another assignment takes place.