Verilog Questions
Master hardware design with Verilog. Practice hardware design and synthesis problems.
| Status | Name | Language | Difficulty | Companies | Action |
|---|---|---|---|---|---|
| Cosmic Ray Shield: Hamming SECDED Codec | Verilog | Hard |  | ||
| Abyss Buffer: Sonar Data FIFO Controller | Verilog | Hard |  | ||
| Sequence Detector — "101" | Verilog | Medium |    | ||
| AXI-Stream Skid Buffer | Verilog | Hard |  | ||
| Round-Robin Arbiter with Priority Override | Verilog | Medium | | ||
| Abyss-1 Explorer | Verilog | Medium | |||
| Mars Rover | Verilog | Medium | | ||
| Tomasulo Reservation Station Entry | Verilog | Hard | | ||
| LRU (Least Recently Used) Cache | Verilog | Medium | | ||
| The Night of the Sold-Out Show | Verilog | Hard | |||
| World Cup Final | Verilog | Hard | |||
| Three Pulses | Verilog | Medium | | ||
| Second Largest Number | Verilog | Medium | | ||
| Binary to Gray Conversion | Verilog | Medium | | ||
| Arithmetic Logic Unit (ALU) | Verilog | Easy | | ||
| Divisible by N | Verilog | Hard | |||
| Triangular Wave Generator | Verilog | Hard | | ||
| Divisible by 5 | Verilog | Hard | | ||
| Priority Encoder - 3bits | Verilog | Hard | | ||
| Verilog Operators | Verilog | Easy | |||
| Verilog Data Types | Verilog | Easy | |||
| Verilog Hello World | Verilog | Easy | |||
| Mux using 2*1 Mux | Verilog | Easy | |||
| Decoder - gate, data flow and behavioral design | Verilog | Easy | |||
| UNIVERSAL GATE - NOR | Verilog | Easy | |||
| UNIVERSAL GATE - NAND | Verilog | Easy | |||
| Frequency Divider by 6 | Verilog | Easy | | ||
| Frequency Divider by 4 | Verilog | Easy | |||
| Frequency Divider by 3 | Verilog | Easy | |||
| Frequency Divider by 2 | Verilog | Easy | |||
| Frequency Divider by 5 | Verilog | Easy | |||
| Full Adder | Verilog | Easy | |||
| Number of 1's | Verilog | Easy | |||
| Fibonacci Sequence Generatorc | Verilog | Easy | |||
| Negative Edge Detector | Verilog | Easy | | ||
| Positive Edge Detector | Verilog | Easy | |||
| Odd value counter | Verilog | Easy | | ||
| MUX | Verilog | Easy | |||
| karnaugh map | Verilog | Easy | |||
| AND Gate | Verilog | Medium |