MCQ Questions
Test your semiconductor and VLSI fundamentals with our curated multiple-choice questions.
| # | Status | Question | Action |
|---|---|---|---|
| 1 | Aptitude - Clock Synchronization Puzzle Aptitude | ||
| 2 | Physical Design Technique Physical Design - Antenna Effect | ||
| 3 | Setup Slack Calculation With Jitter STA - Setup Slack | ||
| 4 | Clock Domain Crossing - 2 CDC - Digital Design | ||
| 5 | Multi Core Cache Coherence Computer Arch | ||
| 6 | Direct-Mapped Address Field Computer Arch | ||
| 7 | Mealy FSM Sequence Detector Digital Design | ||
| 8 | Digital Design - Inverter Digital Design | ||
| 9 | Metastability Window Static timing Analysis - Metastability | ||
| 10 | Setup Slack3 Static Timing Analysis | ||
| 11 | Transistor Condition Analog Design | ||
| 12 | Max Frequency2 Static Timing Analysis | ||
| 13 | Data Hazard Computer Arch | ||
| 14 | Differential Pair Vs Single Ended Amplifier Analog Design | ||
| 15 | D-Flip Flop Count Digital Design | ||
| 16 | Divider Logic Digital Design - Clock Divider | ||
| 17 | Routing Congestion and Track Assignment Physical Design - Routing | ||
| 18 | CTS - Optimization Physical Design - CTS | ||
| 19 | Hold Time Violation with Clock Skew STA - Hold slack | ||
| 20 | Setup Slack with On-Chip Variation (OCV) STA - Setup Slack | ||
| 21 | Multi Bit Synchronization CDC - Digital Design | ||
| 22 | FSM Bubble State Elimination FSM - Digital Design | ||
| 23 | Memory Hierarchy and Page Table Walk Computer Arch | ||
| 24 | Cache Coherency and Bandwidth Computer Arch | ||
| 25 | UVM - Connect Phase UVM | ||
| 26 | UVM - Phases UVM | ||
| 27 | UVM - top down phases UVM | ||
| 28 | UVM - connect_phase() UVM | ||
| 29 | System Verilog Looping (Overflow/Rollover Concept) | ||
| 30 | System Verilog - class operators | ||
| 31 | CMOS Pass Transistor | ||
| 32 | Verilog: System Tasks | ||
| 33 | SystemVerilog Combination Logic Modelling | ||
| 34 | Clock Generation | ||
| 35 | CMOS Power | ||
| 36 | Sequential Logic : Race-Condition | ||
| 37 | CMOS Device Physics | ||
| 38 | Verilog Procedural Assignments | ||
| 39 | Setup and Hold | ||
| 40 | Sequence Generator | ||
| 41 | Via Resistance and Yield Optimization | ||
| 42 | Electromigration Limits | ||
| 43 | Randomization Constraints | ||
| 44 | Crosstalk Induced Delay | ||
| 45 | ICG Timing | ||
| 46 | Effective Bandwidth | ||
| 47 | TLB Tag Width | ||
| 48 | Area Trade Off | ||
| 49 | Worst Setup Slack | ||
| 50 | Scan Shift Power Budgeting | ||
| 51 | Antenna Effect Limits | ||
| 52 | Clock Tree Network Power | ||
| 53 | Data Transfer Latency | ||
| 54 | Hex Sequence | ||
| 55 | Clock Edge Synchronization | ||
| 56 | Physical Design Issue | ||
| 57 | Write Buffer | ||
| 58 | Current Mirror2 | ||
| 59 | MOSFET vs BJT | ||
| 60 | Runtime | ||
| 61 | Voltage Transient | ||
| 62 | Peak Voltage | ||
| 63 | Assertion Pass | ||
| 64 | Borrowed Time | ||
| 65 | Invalid States | ||
| 66 | PMOS Width | ||
| 67 | Thermal Comparison | ||
| 68 | Sequence Objection | ||
| 69 | Race Condition | ||
| 70 | Time available | ||
| 71 | CMOS Power Dissipation | ||
| 72 | Sequential Logic Race | ||
| 73 | Pass Transistors | ||
| 74 | Negative Hold Time | ||
| 75 | Odd Clock Frequency and Duty Cycle | ||
| 76 | GLS Coverage | ||
| 77 | Assertion | ||
| 78 | Safe Clock | ||
| 79 | Moore Machine | ||
| 80 | WORST Case Sizing | ||
| 81 | Stalls Count | ||
| 82 | Jug | ||
| 83 | Crosstalk and Shielding | ||
| 84 | Coverage Analysis | ||
| 85 | Max Freq | ||
| 86 | CDC Pointers | ||
| 87 | Cache Aliasing | ||
| 88 | Server Crash | ||
| 89 | SV Constraints | ||
| 90 | Logic Sizing | ||
| 91 | CPI | ||
| 92 | Antenna | ||
| 93 | Verilog Assignments | ||
| 94 | Bias Region | ||
| 95 | Sum of Products | ||
| 96 | Current Mirror | ||
| 97 | Max Delay | ||
| 98 | MOSFET | ||
| 99 | Clock Tree Synthesis | ||
| 100 | Probability |