Scenario: A processor has a 2-way set-associative L1 cache. The access time is 1 cycle for a hit and 50 cycles for a miss (penalty to fetch from L2). You observe that a specific matrix multiplication algorithm has a hit rate of 90%. You decide to double the cache size, which increases the hit rate to 95% but increases the hit time to 1.2 cycles due to larger decoder logic and wiring delays, and also increases the miss penalty to 100 cycles for a miss.
Question: What is the impact on the Average Memory Access Time (AMAT)?
AMAT (scenario1) = 1 + (0.1 × 50) = 6
AMAT (scenario2) = 1.2 + (0.05×100) = 6.2
In this case, even after increasing the memory size, AMAT worsens by 0.2 cycles
