Assertion

Analyze the following SystemVerilog Assertion (SVA) property: property p_req_ack; @(posedge clk) req |-> ##[1:3] ack; endproperty. If the signal req goes high exactly at T=10ns (coinciding with a clock edge), what is the acceptable time window for ack to go high to satisfy this assertion? (Assume a clock period of 10ns).