Assertion Pass
In SystemVerilog Assertions (SVA), a verification engineer writes the following property: A |=> B [*3] ##1 C. Which of the following accurately describes the cycle-by-cycle requirement for this assertion to pass?
In SystemVerilog Assertions (SVA), a verification engineer writes the following property: A |=> B [*3] ##1 C. Which of the following accurately describes the cycle-by-cycle requirement for this assertion to pass?