A 5-stage classic RISC pipeline (IF, ID, EX, MEM, WB) has full operand forwarding implemented. A branch instruction is resolved in the EX stage. The instruction mix is 20% branches, of which 60% are taken. What is the overall CPI (Cycles Per Instruction) assuming a base CPI of 1.0 and no other hazards?
Since the branch is resolved in the EX stage, the processor has already fetched two instructions (in IF and ID) after the branch. If the branch is taken, these 2 instructions must be flushed, resulting in a 2-cycle penalty. If not taken, there is no penalty. Penalty frequency = 20% (branches) 60% (taken) = 0.12. Penalty cycles = 0.12 2 = 0.24. Total CPI = Base CPI + Stall CPI = 1.0 + 0.24 = 1.24.
