A processor features a Virtually Indexed, Physically Tagged (VIPT) L1 data cache. The system uses a 4 KB virtual page size. The L1 cache is 32 KB in total capacity, 4-way set associative, with a 64 Byte cache line size. Does this architecture suffer from cache aliasing, and if so, how many bits of the virtual address cause the overlap?
Cache aliasing in VIPT caches occurs when the bits used to index the cache exceed the bits defining the page offset (meaning the index uses bits that can change during virtual-to-physical translation). Page size is 4 KB (2^12 bytes), so the page offset is 12 bits. The cache has 32 KB / (4 ways * 64 Bytes) = 128 sets. Indexing 128 sets requires 7 bits. The block offset for 64 Bytes requires 6 bits. Total bits needed for cache access = 7 (index) + 6 (offset) = 13 bits. Since 13 bits > 12 bits of the page offset, 1 bit of the virtual address overlaps with the translated physical page number, causing exactly 1 bit of aliasing.
