Cache Coherency and Bandwidth

A multi-core processor uses a write-back L1 data cache with a MESI protocol and a 64-byte line size. Core 0 and Core 1 both have a shared copy (State: S) of a cache line containing an array. Core 0 executes a loop writing a 4-byte integer to its local copy of index 0 of the array every 10 cycles, while Core 1 continuously reads a 4-byte integer from index 1 of the same array every 5 cycles. Assuming zero structural hazards and a bus arbitration latency of 2 cycles, what is the primary architectural bottleneck causing severe performance degradation?