A critical timing path between FF_Launch and FF_Capture is failing setup by -0.2 ns. Hold timing on this identical path has a massive positive slack of +0.5 ns. What intentional Clock Tree Synthesis (CTS) adjustment (known as Useful Skew) can safely resolve this setup violation without modifying the combinational logic?
Setup slack = Required Time - Arrival Time. By intentionally delaying the clock arrival at the capture flop (FF_Capture), we push the Required Time later, effectively "stealing" time from the subsequent timing path and donating it to our failing path. Adding 0.3 ns of delay to FF_Capture improves the setup slack by +0.3 ns (fixing the -0.2 ns violation). This shifts the hold check later as well, degrading hold slack by 0.3 ns. Since we had +0.5 ns hold slack, it remains safe at +0.2 ns.
