A fast clock domain (CLK_A, 1 GHz) sends a single-cycle pulse to a slow clock domain (CLK_B, 100 MHz). A standard 2-flop synchronizer is used. What is the most likely failure scenario?
Explanation: This is a classic "Pulse Width" violation in Clock Domain Crossing (CDC). The CLK_A pulse lasts 1ns, but CLK_B only samples every 10ns. There is a high probability that CLK_B will never "see" the pulse because it rises and falls between CLK_B sampling edges. To fix this, you must "stretch" the pulse in the source domain or use a handshake/toggle-based synchronizer.
