An asynchronous FIFO uses an 8-bit pointer to track the write address. The designer crosses this pointer directly from the 200 MHz write domain to the 100 MHz read domain using a bank of eight standard 2-flop synchronizers. During silicon validation, the FIFO frequently drops data. Why is passing a multi-bit binary counter through standard synchronizers architecturally flawed?
Passing multi-bit binary signals across asynchronous domains using simple synchronizers is a fatal CDC error. When a binary counter transitions (e.g., from 011 to 100, where 3 bits flip simultaneously), unequal routing delays (skew) to the synchronizer flops mean the capture clock might sample the bits at different times. It could capture 000, 111, or any random intermediate value, completely corrupting the FIFO logic. This is why Gray code (where only exactly 1 bit changes per transition) is mandatory for asynchronous FIFO pointers.
