Clock Domain Crossing - 2

You are designing an SoC where a 1-bit active-high control pulse originates in a fast DSP clock domain running at 500 MHz (2ns period) and needs to be captured by a slow peripheral domain running at 100 MHz (10ns period). If the pulse in the fast domain is exactly one clock cycle wide (2ns), what is the primary risk of using a standard 2-flop synchronizer in the slow domain, and how should it be mitigated?