In a synchronous datapath, the launch flip-flop and capture flip-flop are clocked by the same source, but there is a positive clock skew of 1.0 ns (the clock arrives at the capture flop 1.0 ns later than the launch flop). The clock period is 5.0 ns. The clock-to-Q delay Tcq is 1.0 ns, setup time Tsetup is 0.5 ns, and hold time Thold is 0.5 ns. What is the maximum allowable combinational delay T{comb,max} and minimum allowable combinational delay T{comb,min} to avoid setup and hold violations?
