CMOS Device Physics
In CMOS logic design, it is a known rule that an NMOS transistor passes a strong '0' but a weak '1'. What is the fundamental device physics reason for this degraded high logic level?
In CMOS logic design, it is a known rule that an NMOS transistor passes a strong '0' but a weak '1'. What is the fundamental device physics reason for this degraded high logic level?