Calculate the logical effort of a 3-input NOR gate. Assume a standard CMOS inverter has a PMOS width of 2 and an NMOS width of 1 (total input capacitance = 3) for equal rise and fall times. For the NOR gate, size the transistors to match the worst-case drive strength of this reference inverter.
For a 3-input NOR gate to match the pull-down strength of an inverter with NMOS=1, each parallel NMOS must be size 1. To match the pull-up strength of the inverter with PMOS=2, the three series PMOS transistors must each be size 3 * 2 = 6. The total input capacitance per input pin is PMOS + NMOS = 6 + 1 = 7. The logical effort is the ratio of this input capacitance to the reference inverter's capacitance (3). Thus, Logical Effort = 7 / 3.
