A verification engineer writes a SystemVerilog covergroup for a 3-bit unsigned transaction ID variable txn_id. The coverpoint specifies two explicit bins: bins lower_half = {[0:3]}; bins upper_half = {[4:7]};. During a constrained random test, txn_id is randomized and driven with the sequence: 1, 3, 2, 1. What is the resulting bin coverage for this specific coverpoint at the end of the test?
The coverpoint defines exactly two bins: lower_half (covering values 0,1,2,3) and upper_half (covering values 4,5,6,7). The driven sequence (1, 3, 2, 1) only contains values that fall into the lower_half bin. The upper_half bin is never hit. Therefore, 1 out of 2 total bins is covered, resulting in a bin coverage of 50%.
