Coverage Analysis

A verification engineer writes a SystemVerilog covergroup for a 3-bit unsigned transaction ID variable txn_id. The coverpoint specifies two explicit bins: bins lower_half = {[0:3]}; bins upper_half = {[4:7]};. During a constrained random test, txn_id is randomized and driven with the sequence: 1, 3, 2, 1. What is the resulting bin coverage for this specific coverpoint at the end of the test?