During physical routing, two long, parallel metal traces on layer M5 suffer from severe cross-coupling capacitance (Cc). Net A is a high-speed clock (the aggressor). Net B is a critical static control signal (the victim) meant to hold a steady logic 0. When Net A transitions from 0 to 1, what electrical phenomenon occurs on Net B, and what is the standard physical design remedy?
When the aggressor (Net A) transitions from 0 to 1, the cross-coupling capacitance (Cc) acts as a high-pass filter, injecting charge onto the victim net (Net B). Because Net B is at logic 0, this charge creates a positive voltage bump (glitch). If this glitch crosses the threshold voltage of downstream logic, it causes a functional failure. The standard routing fix is to increase the spacing between the nets, or optimally, drop a grounded shielding wire (VSS) between them to terminate the electric field lines and decouple the nets.
