If a flip-flop has a setup time of 2ns and a hold time of 1ns, when must the input data be stable?
Setup Time (Tsu = 2 ns): The data must be ready and "waiting" at the input for at least 2ns before the clock edge arrives. This means the data must be stable for the entire duration from t = -2ns to t = 0 (the clock edge)
Hold Time (Th = 1 ns): Once the clock edge arrives, the data must stay exactly where it is for at least 1ns after the edge to ensure the internal circuitry has fully "latched" it.
The input data must be stable during the entire window formed by these two values.
Stability Requirement: The data must be stable from 2ns before the clock edge until 1ns after the clock edge.
If the clock edge occurs at time t = 0:
Start of Stability: t = -2ns
End of Stability: t = +1ns
Total Duration: 3ns (This is the "Aperture Time").
If the data signal flips its state (0 to 1 or 1 to 0) within that 3ns window, the flip-flop enters a state called Metastability. The output might:
Become stuck at an intermediate voltage (neither 0 nor 1).
Oscillate wildly.
Take a long time to settle to a final value, potentially causing errors in the rest of your circuit.
Term | Value | Meaning |
Setup Time | 2 ns | Data must arrive before the edge. |
Hold Time | 1 ns | Data must stay after the edge. |
Stability Window | 3 ns total | The period where any change is "illegal." |
