High switching activity in a localized cluster of a chip causes a localized dynamic IR drop of 10% on the VDD rail. According to first-order transistor delay models, how does this specifically impact the Static Timing Analysis (STA) of cells located in this cluster?
A voltage drop (IR drop) starves transistors of current, increasing their transition times and overall propagation delay. Increased delay on the data path makes it harder to meet setup time (degrading setup slack) but effectively delays the data arrival, making hold violations less likely (improving hold slack).
