Consider the following Verilog code intended to model a two-stage pipeline register. What is the most likely synthesis result for q1 and q2?
always @(posedge clk) begin
q1 = d; // Stage 1
q2 = q1; // Stage 2
endAs blocking statements are used inside the always block. On a single clock edge - d value will be transferred to q1 and q1 value will be transferred to q2 once first operation is done, therefore logically q2 is getting d value itself in every clock edge. Therefore during synthesis flop will be optimized.