A Moore State Machine uses a combinational output decoder. If the state transitions from 011 to 100 and the output logic is Out = S2 & (~S1) & (~S0), what phenomenon might occur at the output during the transition?
Explanation: When moving from 011 to 100, all three bits change. Because of physical wire delays, they won't change at the exact same picosecond. For a brief moment, the decoder might see an intermediate state like 111 or 010, causing the output to flicker (glitch) before settling to its correct value. This is why high-speed designs often register the outputs of an FSM.
