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FSM Bubble State Elimination
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(A) The FSM will recover to So within exactly 1 clock cycle.
(B) The FSM may lock into a state where multiple state bits remain active, creating conflicting output assertions.
(C) The FSM registers will enter a metastable condition due to voltage contention.
(D) The FSM will automatically reset because one-hot decoders reject multi-bit hot states.
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