A data path operates on a 1 GHz clock with a 40% duty cycle. The clock rises at 0 ps, falls at 400 ps, and rises again at 1000 ps. The data launches from a flip-flop triggered on the falling edge and is captured by a flip-flop triggered on the very next rising edge. Assuming zero clock skew and a capture setup time of 30 ps, what is the available time (Data Required Time before setup) for the combinational logic and clock-to-Q delay?
The launch edge (falling) occurs at 400 ps. The capture edge (next rising) occurs at 1000 ps. The total time between launch and capture edges is 1000ps - 400ps = 600ps. The setup time must be subtracted from this window to find the maximum allowed data delay: 600ps - 30ps = 570ps.
