An out-of-order processor is executing the following instructions:
MUL R1, R2, R3 (Takes 5 cycles)
ADD R1, R4, R5 (Takes 1 cycle)If the processor executes Instruction 2 and writes its result to R1 Before Instruction 1 finishes writing its result to R1, Which hazard has occurred, and how is it typically solved in hardware?
WAW is a "Name Dependency" solved by mapping architectural registers to a larger physical register file (Register Renaming)