A highly congested, densely packed region of a SoC experiences significant dynamic IR drop (voltage droop) during normal operation. How does this localized voltage drop directly interact with the Static Timing Analysis (STA) of the standard cells residing in this region?
CMOS switching delay is inversely proportional to the supply voltage (Vdd). A dynamic IR drop effectively starves the transistors in that region of voltage, reducing their drive current. This slower transition time inherently increases the propagation delay of combinational logic gates. Extended delays on data paths push the data arrival time later into the clock period, directly increasing the likelihood of setup timing violations.
