Logic Sizing

You are sizing a static CMOS compound gate for the function Y = ~(A * (B + C)). The base reference inverter has sizing Wn = 1 and Wp = 2. To ensure the worst-case rise and fall times match the reference inverter, what must be the channel widths of the PMOS transistor driven by input A (Wp_A) and the NMOS transistor driven by input A (Wn_A)?