You are sizing a static CMOS compound gate for the function Y = ~(A * (B + C)). The base reference inverter has sizing Wn = 1 and Wp = 2. To ensure the worst-case rise and fall times match the reference inverter, what must be the channel widths of the PMOS transistor driven by input A (Wp_A) and the NMOS transistor driven by input A (Wn_A)?
For the pull-up network (PUN), the PMOS logic is A in parallel with (B in series with C). The worst-case pull-up is either A alone, or B and C together. To match the base Wp=2, Wp_A must be 2. For the pull-down network (PDN), the NMOS logic is A in series with (B in parallel with C). The worst-case pull-down is A and B (or A and C) in series. To match the base Wn=1 with two transistors in series, they must both be sized to 2. Therefore, Wn_A = 2.
