An Edge AI accelerator features a 4-way set associative L1 cache using a strict True LRU (Least Recently Used) replacement policy. A matrix multiplication kernel repeatedly loops through 5 distinct memory blocks (Block A, B, C, D, and E). Due to unfortunate address aliasing, all 5 blocks map to the exact same cache set. Assuming the cache is initially empty, what will the cache hit rate be after 100 iterations of accessing the sequence A-B-C-D-E (500 total accesses)?
Because the set only holds 4 blocks, accessing 5 blocks sequentially causes complete cache thrashing.
Iteration 1: A, B, C, D miss and fill the cache. The access to E misses and evicts A (the least recently used). Cache state: [E, D, C, B].
Iteration 2: The access to A misses and evicts B. Cache state: [A, E, D, C]. The access to B misses and evicts C.
Every single access requests the exact block that was evicted 4 steps prior. The hit rate will be exactly 0%.
