In a synchronous digital circuit, the launching flip-flop has a clock-to-q delay (Tcq) of 0.3 ns and the capturing flip-flop has a setup time (Tsu) of 0.2 ns. If the clock period is 2.0 ns and there is a positive clock skew of 0.15 ns (i.e., the clock arrives at the capturing flop 0.15 ns later than at the launching flop), what is the maximum permissible delay of the combinational logic path between the two flops to avoid a setup violation?
The setup timing equation is: T_clock_period + T_skew >= Tcq + T_logic + Tsu. A positive skew (when the capture clock is delayed) helps meet the setup requirement by providing more time for the data to arrive. Rearranging the formula to find the maximum logic delay (T_logic): T_logic <= T_clock_period + T_skew - Tcq - Tsu. Plugging in the values: T_logic <= 2.0 ns + 0.15 ns - 0.3 ns - 0.2 ns = 1.65 ns.
