Max Frequency2

In a synchronous design, the data path delay from a source flip-flop (FF1) to a destination flip-flop (FF2) is 5ns. The clock-to-Q delay of FF1 is 0.5ns, and the setup time for FF2 is 1ns. If there is a positive clock skew of 0.5ns (FF2 receives the clock 0.5ns later than FF1), what is the maximum clock frequency at which this path will operate without a setup violation?