Mealy FSM Sequence Detector

A verification engineer is validating a Mealy FSM that detects the serial sequence 1101 with overlapping allowed. The FSM asserts found=1 based on the current state AND the current input (simultaneously, not one cycle later). The input stream applied at consecutive clock edges is: 1 1 0 1 1 0 1. At which clock cycles is found asserted HIGH? (1-indexed, output evaluated when input is applied)