During a processor read miss, if another cache holds the data in the 'M' state, what actions occur?
When a cache requests a block and another cache has it in the 'M' state (modified/dirty), the 'M' cache is responsible for supplying the data. The protocol dictates a three-way transfer: the data is sent to the requesting cache and written back to main memory. Since two caches now hold the same, consistent copy of the data, both caches must transition to the 'S' (Shared) state
