What is the primary reason for a cache line to enter the 'I' (Invalid) state in the MESI protocol?
A cache line enters the 'I' (Invalid) state primarily because the cache snooped a bus transaction indicating that another processor has initiated a write operation to that same memory block. The originating cache sends a signal that forces all other caches holding the block to invalidate their copies, ensuring the system only relies on the new, modified data held by the writing cache.
