Which of the following best describes metastability in a flip-flop?
Metastability occurs when a flip-flop samples data too close to the clock edge (setup or hold violation).
The output enters an indeterminate voltage level between logic 0 and 1, and may take an unpredictable amount of time to resolve to a valid logic level.
It cannot be eliminated entirely — only the probability of it causing a system failure can be reduced using synchronizers.
