Multi Core Cache Coherence

Core A and Core B each have a private L1 data cache with 64-byte cache lines. Core A repeatedly writes to a 32-bit integer variable X, while Core B repeatedly writes to a 32-bit integer variable Y. Both variables X and Y happen to be allocated adjacently in memory at addresses 0x1000 and 0x1004, respectively. What specific performance-degrading phenomenon occurs here, and how does the MESI protocol react?