You are sizing a static CMOS compound gate implementing the logic function F = (a. (b + c))’. A standard unit inverter has an NMOS size of W/L = 2 and a PMOS size of W/L = 4. To achieve a worst-case pull-down transition time equal to that of the unit inverter, what must the NMOS widths (Wa, Wb, Wc) be, assuming L is constant?
The Pull-Down Network (PDN) consists of transistor A in series with the parallel combination of B and C. The worst-case resistance path occurs when A is ON, and only ONE of the parallel transistors (B or C) is ON. This puts two transistors in series. To match the resistance of the unit NMOS (W=2), each transistor in the series path must have half the resistance, meaning double the width. Therefore, Wa = 4 and Wb = 4. By symmetry for the worst-case path through C, Wc = 4$.
