In a 7nm design using POCV (Parametric On-Chip Variation), why is a "flat" 10% derate factor considered insufficient compared to older 28nm nodes?
Explanation: In advanced nodes, variation is statistical. A flat derate applies the same penalty regardless of the number of gates. However, in a long logic chain, variations tend to average out (statistical "cancellation"). POCV uses a distance-based and cell-count-based approach to provide a more realistic (and less "fat") timing margin.
