In a superscalar out-of-order processor implementing Tomasulo's algorithm, an instruction is decoded and issued, but its required source operands are not yet available in the register file. Where is the instruction held while waiting, and what specific identifier does it monitor on the Common Data Bus (CDB) to capture its operands?
In Tomasulo's algorithm, an issued instruction waits in a Reservation Station. To resolve data dependencies without stalling, it monitors the Common Data Bus for the unique Tag (the ID of the producing Reservation Station) assigned to the instruction that will generate its missing operand. Once that tag broadcasts on the CDB, the waiting instruction grabs the data.
