A balanced clock tree is synthesized for an SoC at the TT (Typical-Typical) process corner, achieving a pristine near-zero clock skew. However, during Multi-Mode Multi-Corner (MMMC) signoff, analysis at the FF (Fast-Fast) corner reveals massive clock skew leading to widespread hold violations. What is the primary physical phenomenon causing this tree balance to break across corners?
A perfectly balanced tree at one corner relies on exact delay matching of thousands of buffers. Across the die surface, process parameters (like oxide thickness and channel length) vary slightly. This is On-Chip Variation (OCV). Different branches of the clock tree will scale down at slightly different rates when shifting to the FF corner. This differential scaling breaks the delicate balance achieved at the TT corner, introducing significant skew
