In a 5nm physical design, a specific modular block exhibits heavy localized routing congestion (short-circuit hotspots) in the initial global route. The core cell utilization in that specific localized bounding box is 90%. Without altering the RTL logic, what is the primary physical design step to alleviate this?
Localized routing congestion in a highly utilized area means too many pins exist in a small geometric area, overwhelming the available routing tracks. Applying a partial placement blockage (or density screen) forces the placement engine to spread the cells out, reducing pin density per square micron, which naturally alleviates the localized routing track shortage.
