A processor increases its pipeline depth from 12 to 20 stages to achieve a higher clock frequency. If the branch misprediction rate remains constant at 5%, what is the most significant impact on the IPC (Instructions Per Cycle)?
Pipelining increases frequency but also increases the "penalty" for errors. When a branch is mispredicted in a deeper pipeline, more instructions must be flushed (20 vs. 12), leading to more "bubbles" and lower average IPC.
