In a standard 5-stage RISC pipeline (IF, ID, EX, MEM, WB), which of the following instruction sequences cannot be resolved by simple hardware forwarding and require a stall?
Answer: B
Explanation: This is the "Load-Use" hazard. The data for LW is only available at the end of the MEM stage, but the following ADD needs it at the start of the EX stage. Forwarding cannot go "backwards in time," so a 1-cycle stall is mandatory.
