Consider a 5-stage RISC pipeline (IF, ID, EX, MEM, WB) without data forwarding. If the instruction sequence is ADD R1, R2, R3 followed immediately by SUB R4, R1, R5, how many stall cycles are required to ensure the correct value of R1 is used? Assuming register write happens on positive edge of clock and register read happens on negative edge of clock.
Instructions:
ADD R1, R2, R3
SUB R4, R1, R5
SUB needs R1, which is produced by the ADD.
This is a RAW (Read After Write) data hazard.
Without stalls, the pipeline would look like this:
Cycle | ADD | SUB |
|---|---|---|
1 | IF | |
2 | ID | IF |
3 | EX | ID |
4 | MEM | EX |
5 | WB | MEM |
But SUB reads registers in ID stage.
So it tries to read R1 in cycle 3.
However:
ADD writes R1 only in cycle 5
So SUB would read the old value → incorrect.
We must delay the ID stage of SUB until cycle 5.
Original:
SUB ID → cycle 3Needed:
SUB ID → cycle 5So we need:
cycle 3 → stall
cycle 4 → stall
cycle 5 → IDThat means 2 stall cycles.