Given a register-to-register path where the source clock (Clk1) arrives at 100ps and the destination clock (Clk2) arrives at 150ps. If the data path delay is 800ps and the clock period is 1000ps, what is the effect of this skew on the Setup Slack?
Positive skew (where the destination clock is delayed relative to the source) effectively gives the data more time to arrive at the destination flip-flop. The setup equation is Tcycle + Tskew > Tcq + Tlogic + Tsetup. Here, Tskew = +50ps, which increases the slack.
