A 5-stage RISC pipeline (IF, ID, EX, MEM, WB) executes the following instruction sequence: ADD R1, R2, R3, SUB R4, R1, R5, AND R6, R1, R7. If the processor architecture features full data forwarding (bypass) from both the EX/MEM and MEM/WB pipeline registers, how many stall cycles are introduced due to data hazards in this exact sequence?
The ADD instruction produces the result for R1 at the end of its EX stage (stored in the EX/MEM register). The SUB instruction needs R1 at the beginning of its EX stage. Because SUB is immediately after ADD, its EX stage aligns exactly with the clock cycle after ADD's EX stage. The full forwarding path routes R1 from EX/MEM directly to the EX ALU inputs, satisfying SUB. The AND instruction needs R1 one cycle later, which is forwarded from the MEM/WB register. Zero stalls are required.
