Stalls Count

A 5-stage RISC pipeline (IF, ID, EX, MEM, WB) executes the following instruction sequence: ADD R1, R2, R3, SUB R4, R1, R5, AND R6, R1, R7. If the processor architecture features full data forwarding (bypass) from both the EX/MEM and MEM/WB pipeline registers, how many stall cycles are introduced due to data hazards in this exact sequence?