What is the primary function of logic synthesis in the VLSI design flow?
Synthesis takes RTL written in Verilog or SystemVerilog and maps it to actual gates (AND, OR, flip-flops, etc.) from a standard cell library. The output is a gate-level netlist. This is one of the most important steps in the front-end design flow and is performed by tools like Synopsys Design Compiler or Cadence Genus.
