In a SystemVerilog class, a 3-bit variable addr is declared as randc. If an object of this class is randomized 10 times in a loop, which of the following statements is strictly true about the sequence of generated values?
The randc (random cyclic) modifier in SystemVerilog guarantees that all possible values in the variable's range (for 3 bits, 0 through 7) are generated exactly once before any value is repeated. Therefore, the first 8 randomizations will yield 8 unique values.
