A designer writes the following Verilog code. What will a synthesis tool most likely infer from this always block?
always @(sel or a or b) begin
if (sel)
q_out = a;
else
q_out = b;
endThis always block describes purely combinational logic. The sensitivity list includes all inputs sel, a, b), and the output q_out is assigned a value in all possible branches of the if-else statement. This structure directly maps to a 2-to-1 multiplexer, where sel chooses between input a and input b.