A high-performance server processor employs a 2-level TLB hierarchy (L1 and L2) ahead of a 4-level page table walk in virtual memory. An application processing massive Edge AI datasets experiences an L1 TLB miss rate of 5% and an L2 TLB miss rate of 20% (of the misses reaching it). If an L1 TLB hit takes 1 cycle, an L2 TLB hit takes 5 cycles, and one page walk takes 100 cycles, what is the average memory access time (AMAT) for address translation alone?
## AMAT for Address Translation (2-Level TLB Hierarchy)
Given:
- L1 TLB hit time = 1 cycle
- L1 TLB miss rate = 5%
- L2 TLB hit time = 5 cycles
- L2 TLB miss rate (of accesses reaching it) = 20%
- Page walk time = 100 cycles
### Formula
AMAT = T_L1 + MissRate_L1 × (T_L2 + MissRate_L2 × T_pagewalk)
### Step 1 — Cost of falling through to page walk
T_L2 + MissRate_L2 × T_pagewalk = 5 + (0.20 × 100) = 5 + 20 = 25 cycles
### Step 2 — Weight by L1 miss rate and add L1 hit time
AMAT = 1 + (0.05 × 25) = 1 + 1.25 = 2.25 cycles
### Answer
AMAT for address translation = 2.25 cycles
