CTS Flow

After understanding the need for CTS and different clock distribution structures, let's understand the basic steps involved in the Clock Tree Synthesis process.

1. Clock Sink Identification

The first step is to identify all the clock sinks in the design.

Clock sinks are the clock pins of sequential elements such as flip-flops that need to receive the clock signal.

The CTS tool identifies these sinks along with their physical locations and clock connectivity.

2. Clock Tree Building

Once the clock sinks are identified, the tool builds the clock distribution network by inserting clock buffers and inverters at appropriate locations.

Nearby clock sinks are grouped together to form clusters.
Clock buffers are inserted at different levels to distribute the clock to these clusters.
The clock network is built while considering the physical locations of the sinks and electrical constraints.

This creates a buffered clock distribution network from the clock source to all the clock sinks.

3. Clock Tree Balancing

After building the clock tree, the tool works towards balancing the clock arrival times at different clock sinks.

The tool adjusts the clock paths by modifying buffer sizes, buffer locations and the number of buffer stages.

The objective is to minimize excessive clock skew while meeting the required timing constraints.

4. Post-CTS Optimization

Once the clock tree is constructed, the tool performs further optimization to improve the clock network.

Some common optimization activities include:

Skew Optimization: Adjusting clock paths to bring clock arrival times within the required skew limits.
Transition Optimization: Fixing clock nets that violate maximum transition requirements.
Capacitance Optimization: Ensuring that clock nets do not exceed maximum capacitance limits.
Buffer Optimization: Resizing, adding or removing buffers to improve clock distribution.

5. Post-CTS Timing Analysis

Before CTS, timing analysis generally assumes an ideal clock without considering the actual physical clock distribution delays.

After CTS, the clock network has been physically implemented, allowing the tool to perform timing analysis using the propagated clock.

This analysis considers:

Clock buffer and inverter delays.
Clock interconnect delays.
Clock arrival time differences between sequential elements.

Both setup and hold timing are evaluated because the introduction of actual clock path delays can change the timing margins.

Any resulting timing violations are addressed through further optimization.

Summary

The CTS process builds a physical clock distribution network and optimizes it to deliver the clock signal to all sequential elements while meeting timing and electrical requirements.

Overall CTS Flow:

Clock Sink Identification → Clock Tree Building → Clock Tree Balancing → Post-CTS Optimization → Post-CTS Timing Analysis